Sharing local control lines across multiple planes in a memory device
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United States of America Patent
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Feb 3, 2015
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app pub date -
Dec 29, 2011
filing date -
Dec 29, 2011
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Abstract
Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells. Each plane of memory cells includes series strings of memory cells that each have a select gate drain transistor. Control gates of corresponding select gates are coupled together by a shared local control line. Each of a plurality of global control lines are coupled to their corresponding local control line with only a single global select gate.
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