Method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe bridges
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United States of America Patent
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Feb 3, 2015
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app pub date -
Oct 31, 2010
filing date -
Oct 31, 2010
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Abstract
A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.
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