Synchronizing a translation lookaside buffer with an extended paging table

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United States of America Patent

PATENT NO 8949571
SERIAL NO

14070561

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Abstract

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A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Anderson, Andrew V Hillsboro, US 124 4688
Bennett, Steven M Hillsboro, US 93 3242
Neiger, Gilbert Portland, US 289 7052
Rodgers, Dion Hillsboro, US 58 1919
Rust, Camron Hillsboro, US 18 99
Sankaran, Rajesh M Portland, US 111 920
Schoenberg, Sebastian Hillsboro, US 49 1537
Uhlig, Richard Hillsboro, US 71 3240

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