Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device
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United States of America Patent
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Feb 10, 2015
Grant Date -
Feb 21, 2013
app pub date -
Sep 28, 2011
filing date -
Aug 17, 2011
priority date (Note) -
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Abstract
A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.
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