Exposure tolerance estimation method and method for manufacturing semiconductor device

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United States of America Patent

PATENT NO 8956791
APP PUB NO 20140287350A1
SERIAL NO

14027353

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Abstract

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According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kai, Yasunobu Kanagawa-ken, JP 26 70
Masukawa, Kazuyuki Kanagawa-ken, JP 22 68
Yamane, Osamu Kanagawa-ken, JP 16 32

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