Wafer level package resistance monitor scheme

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8957694
APP PUB NO 20130314120A1
SERIAL NO

13477313

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Abstract

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An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.

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Patent Owner(s)

  • AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hu, Kunzhong Irvine, US 73 855
Law, Edward Ladera Rance, US 31 375
Zhong, Chonghua Irvine, US 38 391

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