Semiconductor memory device
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United States of America Patent
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Feb 17, 2015
Grant Date -
Mar 6, 2014
app pub date -
Feb 20, 2013
filing date -
Aug 31, 2012
priority date (Note) -
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Abstract
This semiconductor memory device comprises: a memory cell array configured as an arrangement of memory cells disposed at intersections of a plurality of first lines disposed substantially in parallel and a plurality of second lines disposed to intersect the first lines, each of the memory cells including a variable resistance element; and a control circuit configured to control the memory cell array. The control circuit is configured to change a voltage value of a resetting verify voltage applied for confirming completion of the resetting operation according to a degree of change of resistance of the memory cell when performing the resetting operation to change the memory cell from a low-resistance state to a high-resistance state.
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