System and method for accessing memory

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United States of America Patent

PATENT NO 8959271
APP PUB NO 20140281193A1
SERIAL NO

13835864

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Abstract

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A close proximity memory arrangement maintains a point to point association between DQs, or data lines, to DRAM modules employs a clockless state machine on a DRAM side of the memory controller-DRAM interface such that a single FIFO on the memory controller side synchronizes or orders the DRAM fetch results. Addition of a row address (ROW-ADD) and column address (COL-ADD) strobe reducing latency and power demands. Close proximity point to point DRAM interfaces render the DRAM side FIFO redundant in interfaces such as direct stacked 3D DRAMs on top of the logic die hosting the memory controller. The close proximity point to point arrangement eliminates the DRAM internal FIFO and latency scheme, resulting in just the memory controller internal clock domain crossing FIFOs.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Schaefer, Andre Braunschweig, DE 51 480

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