Facilitating gated stores without data bypass
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United States of America Patent
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Feb 17, 2015
Grant Date -
Jun 17, 2010
app pub date -
Dec 12, 2008
filing date -
Dec 12, 2008
priority date (Note) -
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Abstract
One embodiment of the present invention provides a system that facilitates precise exception semantics for a virtual machine. During operation, the system executes a program in the virtual machine using a processor that includes a gated store buffer that stores values to be written to a memory. This gated store buffer is configured to delay a store to the memory until after a speculatively-optimized region of the program commits. The processor signals an exception when it detects that a load following the store is attempting to access the same memory region being written by the store prior to the commitment of the speculatively-optimized region.
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