Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
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United States of America Patent
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Feb 24, 2015
Grant Date -
Nov 27, 2014
app pub date -
Aug 11, 2014
filing date -
Jan 6, 2012
priority date (Note) -
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Abstract
A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
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