Clock generation using fixed dividers and multiplex circuits
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United States of America Patent
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Feb 24, 2015
Grant Date -
Nov 20, 2014
app pub date -
May 14, 2013
filing date -
May 14, 2013
priority date (Note) -
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Abstract
Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.
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