Address translation through an intermediate address space
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United States of America Patent
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Feb 24, 2015
Grant Date -
Apr 30, 2009
app pub date -
Oct 30, 2007
filing date -
Oct 30, 2007
priority date (Note) -
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Abstract
In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
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