Field-effect transistor (FET) with source-drain contact over gate spacer
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United States of America Patent
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Mar 3, 2015
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app pub date -
Jun 17, 2013
filing date -
Jun 17, 2013
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Abstract
A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.
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