Vertical source/drain junctions for a finFET including a plurality of fins
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United States of America Patent
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Mar 3, 2015
Grant Date -
Apr 17, 2014
app pub date -
Oct 12, 2012
filing date -
Oct 12, 2012
priority date (Note) -
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Abstract
Fin-defining mask structures are formed over a semiconductor material layer. A semiconductor material portion is formed by patterning the semiconductor material layer, and a disposable gate structure is formed over the fin-defining mask structures. After formation of a disposable template layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed by etching center portions of the semiconductor material portion employing the combination of the disposable template layer and the fin-defining mask structures as an etch mask. A first pad region and a second pad region laterally contact the plurality of semiconductor fins. A replacement gate structure is formed on the plurality of semiconductor fins. The disposable template layer is removed, and the first pad region and the second pad regions are vertically recessed. Vertical source/drain junctions can be formed by introducing dopants through vertical sidewalls of the recessed source and second pad regions.
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