Defective P-N junction for backgated fully depleted silicon on insulator MOSFET

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United States of America Patent

PATENT NO 8969966
APP PUB NO 20140312461A1
SERIAL NO

13866077

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Abstract

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Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

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Patent Owner(s)

  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES;GLOBALFOUNDRIES INC.;STMICROELECTRONICS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Kangguo Schenectady, US 3073 29638
Doris, Bruce B Brewster, US 796 13224
Grenouillet, Laurent Rives, FR 64 284
Khakifirooz, Ali Mountain View, US 842 11881
Le, Tiec Yannick Crolles, FR 23 187
Liu, Qing Guilderland, US 483 5041
Vinet, Maud Rives sur Fure, FR 97 1616

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