NROM device with reduced power unit
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United States of America Patent
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Mar 3, 2015
Grant Date -
Aug 29, 2013
app pub date -
Mar 18, 2013
filing date -
Jun 15, 2005
priority date (Note) -
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Abstract
A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.
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