Integrated circuit having MOSFET with embedded stressor and method to fabricate same
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United States of America Patent
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Mar 10, 2015
Grant Date -
Nov 27, 2014
app pub date -
Aug 15, 2013
filing date -
May 22, 2013
priority date (Note) -
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Abstract
A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate.
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