Programmable logic device data rate booster for digital signal processing
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United States of America Patent
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Mar 10, 2015
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N/A
app pub date -
Mar 5, 2012
filing date -
Mar 5, 2012
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Abstract
A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal.
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