Wafer level chip scale package and process of manufacture

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8981464
APP PUB NO 20140239383A1
SERIAL NO

14271168

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Abstract

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Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

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Patent Owner(s)

  • ALPHA & OMEGA SEMICONDUCTOR, LTD.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Feng, Tao Santa Clara, US 160 915
Hébert, François San Mateo, US 86 906
Ho, Yueh-Se Sunnyvale, US 113 2131
Sun, Ming Sunnyvale, US 233 4466

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