Compliant printed circuit semiconductor tester interface
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United States of America Patent
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Mar 17, 2015
Issued Date -
N/A
app pub date -
Jun 28, 2010
filing date -
Jun 29, 2009
priority date (Note) -
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Abstract
A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.
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