Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustment
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United States of America Patent
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Mar 17, 2015
Grant Date -
Jun 20, 2013
app pub date -
Nov 29, 2012
filing date -
Nov 30, 2011
priority date (Note) -
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Abstract
A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
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