Defect injection for transistor-level fault simulation

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United States of America

PATENT NO 8984460
SERIAL NO

13974006

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Abstract

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Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.

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Patent Owner(s)

  • MENTOR GRAPHICS CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sunter, Stephen Kenneth Nepean, CA 10 214

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