Integration of an NPN device with phosphorus emitter and controlled emitter-base junction depth in a BiCMOS process
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United States of America Patent
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Mar 24, 2015
Grant Date -
May 21, 2009
app pub date -
Jan 21, 2009
filing date -
Nov 23, 2004
priority date (Note) -
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Abstract
According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.
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