Circuit, system and method for controlling read latency
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United States of America Patent
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Mar 24, 2015
Grant Date -
Dec 8, 2011
app pub date -
Aug 17, 2011
filing date -
Mar 15, 2007
priority date (Note) -
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Abstract
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.
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