Encoding/decoding processor and wireless communication apparatus
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United States of America Patent
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Mar 24, 2015
Grant Date -
Dec 5, 2013
app pub date -
Feb 7, 2012
filing date -
Feb 10, 2011
priority date (Note) -
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Abstract
An encoding/decoding processor includes a coprocessor that is dedicated to encoding and decoding processes, where the coprocessor comprises: a parameter register that stores externally given operation modes and the settings of generation polynomials; and a calculation circuit that operates on the basis of the operation modes and the generation polynomials and that performs calculations, which are required for the encoding and decoding processes, by a plurality of bits per cycle in a parallel manner, and the coprocessor further comprises memory controllers, which include: address generator circuits for outputting the addresses of the storage devices; FIFO circuits for temporarily storing data; and data packing circuits for making up predetermined numbers of bits of data for output.
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