Performing emulated message signaled interrupt handling

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United States of America Patent

PATENT NO 8996774
APP PUB NO 20140006668A1
SERIAL NO

13534511

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Abstract

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In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chew, Yen Hsiang Penang, MY 87 1184

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