Memory system and bank interleaving method
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United States of America Patent
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Mar 31, 2015
Grant Date -
Sep 26, 2013
app pub date -
Aug 31, 2012
filing date -
Mar 23, 2012
priority date (Note) -
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Abstract
According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.
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