Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates
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United States of America Patent
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Mar 31, 2015
Grant Date -
Oct 23, 2014
app pub date -
Jun 27, 2014
filing date -
Dec 28, 2011
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Abstract
A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.
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