Transaction-level testing of memory I/O and memory device
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United States of America Patent
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Mar 31, 2015
Grant Date -
Apr 3, 2014
app pub date -
Sep 29, 2012
filing date -
Sep 29, 2012
priority date (Note) -
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Abstract
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.
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