Suspend SDRAM refresh cycles during normal DDR operation

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United States of America Patent

PATENT NO 8996942
APP PUB NO 20140177371A1
SERIAL NO

13778636

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.

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Patent Owner(s)

  • AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ellis, Jackson L Fort Collins, US 30 876
Sinha, Shruti Maharashtra, IN 3 42

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