Electronic fuse having an insulation layer
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United States of America Patent
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Apr 7, 2015
Grant Date -
Jul 31, 2014
app pub date -
Jan 31, 2013
filing date -
Jan 31, 2013
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the seed layer causing the seed layer to reflow and fill the first via opening, fill the second via opening, and partially fill the trench opening to form a first via, a second via, and a fuse line, respectively, wherein the seed layer no longer remains along an entire length of a sidewall of the trench opening. The method further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening.
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