Reduced stress TSV and interposer structures
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United States of America Patent
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Apr 7, 2015
Grant Date -
Aug 7, 2014
app pub date -
Mar 11, 2014
filing date -
Jun 8, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
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