Sub-block decoding in 3D memory

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United States of America Patent

PATENT NO 9001584
APP PUB NO 20140241060A1
SERIAL NO

13781016

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Abstract

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Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ha, Chang Wan San Ramon, US 74 723

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