Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

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United States of America Patent

PATENT NO 9003125
APP PUB NO 20130339622A1
SERIAL NO

13523535

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Abstract

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A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ambroladze, Ekaterina M Wappingers Falls, US 49 250
Blake, Michael Wappingers Falls, US 11 27
Bronson, Tim Round Rock, US 7 16
Drapala, Garrett Poughkeepsie, US 2 7
Mak, Pak-kin Poughkeepsie, US 89 1213
O'Neill, Arthur J Poughkeepsie, US 28 137

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