Systems and methods for indirect register access using status-checking and status-setting instructions
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United States of America Patent
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Apr 7, 2015
Grant Date -
Sep 17, 2009
app pub date -
Mar 16, 2009
filing date -
Oct 5, 2004
priority date (Note) -
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Abstract
The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
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