Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
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United States of America Patent
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Apr 14, 2015
Grant Date -
Jun 26, 2014
app pub date -
Oct 7, 2013
filing date -
Nov 20, 2006
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Abstract
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.
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