SRAM global precharge, discharge, and sense
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United States of America Patent
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Apr 14, 2015
Grant Date -
Apr 24, 2014
app pub date -
Oct 18, 2012
filing date -
Oct 18, 2012
priority date (Note) -
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Abstract
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.
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