Verifying processor-sparing functionality in a simulation environment
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United States of America Patent
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Apr 21, 2015
Grant Date -
May 2, 2013
app pub date -
Oct 31, 2011
filing date -
Oct 31, 2011
priority date (Note) -
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Abstract
A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.
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