Bit error rate based wear leveling for solid state drive memory

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United States of America Patent

PATENT NO 9015537
APP PUB NO 20140101499A1
SERIAL NO

14101655

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Abstract

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According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Griffin, Thomas J Salt Point, US 26 398
Vanstee, Dustin J Poughkeepsie, US 26 738

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