Delay time adjusting circuit, method, and integrated circuit
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United States of America Patent
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Apr 28, 2015
Grant Date -
Jun 19, 2014
app pub date -
Dec 11, 2013
filing date -
Dec 17, 2012
priority date (Note) -
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Abstract
A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs.
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