Flash memory read error recovery with soft-decision decode
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United States of America Patent
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Apr 28, 2015
Grant Date -
Jun 12, 2014
app pub date -
Mar 13, 2013
filing date -
Dec 11, 2012
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Abstract
An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.
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