EMBEDDED CHARGE TRAP MULTI-TIME-PROGRAMMABLE-READ-ONLY-MEMORY FOR HIGH PERFORMANCE LOGIC TECHNOLOGY
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United States of America Patent
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May 5, 2015
Grant Date -
May 21, 2015
app pub date -
Nov 20, 2013
filing date -
Nov 20, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (ΔVT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.
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