On-chip interferers for standards compliant jitter tolerance testing
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United States of America Patent
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May 5, 2015
Grant Date -
Nov 14, 2013
app pub date -
Jun 29, 2012
filing date -
May 14, 2012
priority date (Note) -
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Abstract
Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.
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