Method for fabrication of a semiconductor device and structure

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United States of America Patent

PATENT NO 9029173
APP PUB NO 20130095580A1
SERIAL NO

13276312

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Abstract

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A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.

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Patent Owner(s)

  • MONOLITHIC 3D INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cronquist, Brian San Jose, US 284 3809
Or-Bach, Zvi San Jose, US 534 17764
Sekar, Deepak C San Jose, US 220 3440
Wurman, Ze'ev Palo Alto, US 18 2314

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