Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking
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United States of America Patent
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May 12, 2015
Grant Date -
Nov 21, 2013
app pub date -
May 15, 2012
filing date -
May 15, 2012
priority date (Note) -
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Abstract
One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.
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