Adjusting program and erase voltages in a memory device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 12, 2015
Grant Date -
May 1, 2014
app pub date -
Jan 8, 2014
filing date -
Dec 5, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully