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United States of America Patent

PATENT NO 9032103
APP PUB NO 20130097353A1
SERIAL NO

13706575

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Abstract

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A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ajanovic, Jasmin Portland, US 94 2794
Akiyama, James Beaverton, US 38 776
Barry, Peter Ardncrusha, IE 30 440
Bhatt, Ajay V Portland, US 30 1445
Blankenship, Robert G Tacoma, US 120 1211
Das, Sharma Debendra Saratoga, US 191 1591
Falik, Ohad Kfar Saba, IL 92 1940
Harriman, David J Portland, US 139 2344
Mendelson, Avi Haifa, IL 28 507
Muthrasanallur, Sridhar Puyallup, US 51 1131
Pardo, Ilan Ramat Hasharon, IL 69 927
Rodgers, Scott Dion Hillsboro, US 49 830
Rosenbluth, Mark B Uxbridge, US 84 1815
Sethi, Prashant Folsom, US 88 1545
Shamia, Doron Modiin, IL 26 514
Tamari, Eran Ramat Gan, IL 40 584
Vasudevan, Anil Portland, US 175 2375
Wagh, Mahesh Portland, US 117 1485
Weissmann, Eliezer Haifa, IL 186 2264

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