Self aligned contact with improved robustness
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United States of America Patent
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May 19, 2015
Grant Date -
Mar 13, 2014
app pub date -
Sep 13, 2012
filing date -
Sep 13, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.
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