Level shifter with low voltage loss
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United States of America Patent
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May 19, 2015
Grant Date -
Jun 20, 2013
app pub date -
Nov 29, 2012
filing date -
Dec 20, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.
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