Flash memory techniques for recovering from write interrupt resulting from voltage fault
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United States of America Patent
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May 19, 2015
Grant Date -
Sep 18, 2014
app pub date -
Mar 15, 2013
filing date -
Mar 15, 2013
priority date (Note) -
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Abstract
Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.
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